ZHANG Pingping, LI Jinming
（School of Instruments and Electronics, North University of China, Taiyuan 030051, China）
Abstract： In order to solve the low-power design of reed-solomon (RS) code, it is carried out from different design levels such as system architecture, RTL level and gate level, etc. And it is practiced in application specific integrated circuit (ASIC) design. The back-end IC design is combined to study the chip that can realize the RS coding function. At the system architecture level, the multiplication operation of Galois field in the RS coding algorithm has problems such as large amount of data operation and high-power consumption in hardware implementation. A method based on a multiplier factor matrix is proposed to optimize the RS coding algorithm. The data operation is reduced by converting multiplication operation to subtraction operation, so as to reduce power consumption. At the RTL level and gate level, the logic synthesis and back-end implementation are constrained to implement the low power design, and the overall power consumption can be reduced by about 60%. The problem of high-power consumption of IC chip is solved, which leads to the decline of chip performance, affects the normal operation of the chip and provides a new direction for the integrated circuit process.
Key words： reed-solomon (RS) code; low-power design; application specific integrated circuit (ASIC); logic synthesis
References
［1］LI J M, LIU M X, CHENG N P. Optimization of RScoding algorithm and FPGA implementation. Application of Electronic Technology, 2020, 46(2): 76-79+83.
［2］LIU M X.Research and design of RS encoding and decoding based on FPGA. Taiyuan: North University of China, 2020.
［3］YU J. FPGA-based satellite communication channel coding design and engineering implementation. Shijiazhuang: Hebei University of Science and Technology, 2015.
［4］YANG X L, GUO X. Design and implementation of RS coding based on FPGA. Journal of He’nan Electromechanical College, 2016, 24(4): 11-14.
［5］YAN Z W, CHEN S H, ZHANG B P. Implementation of an improved high-speed data transmission platform using RS coding. Application of Single Chip Microcomputer and Embedded System, 2021, 21(5): 79-83.
［6］GE Q J. Low-power design process of CPU module under 7 nm process. Shenyang: Liaoning University, 2022.
［7］CHEN G S, ZHANG X, SHEN L W. Low-power design of CMOS digital integrated circuits. Integrated Circuit Applications, 2021, 38(7): 17-21.
［8］SHI M. Research on low power consumption design of MCU based on 40 nm process. Xi’an: Xidian University, 2021.
［9］ZHANG X. Low-power and high-efficiency power managementsystem applied to IoT SoC chips. Shanghai: East China Normal University, 2022.
［10］CHEN X L. Q-band modulation signal segment circuit CMOS IC design. Chengdu: University of Electronic Science and Technology of China, 2022.
［11］LI K. 3D IC layout and wiring design based on OC8051 chip processor. Xi’an: Xidian University, 2015.
［12］WEI Q C. Research on key technologies in back-end design of ultra-deep submicron ICs. Harbin: Harbin Institute of Technology, 2008.
［13］LUO Z H, QUAN J G, YANG H Z. Realization of back-end design of EOS chip based on hierarchical method. Microcomputer Information, 2008(14): 5-7.
［14］LI J M, JIA B X. Hardware implementation and IC research of LDPC encoding. Application of Single Chip Microcomputer and Embedded System, 2022, 22(4): 65-69.
RS编码的低功耗设计及ASIC研究
张萍萍， 李锦明
（中北大学 仪器与电子学院， 山西 太原 030051）
摘要：为解决里所（Reed-solomon， RS）编码的低功耗设计， 从系统架构、 RTL级、 门级等不同设计层级进行分析， 并在专用集成电路（Application specific integrated circuit， ASIC）设计中加以实践。 基于低功耗设计将前端RTL级设计与后端IC设计结合起来， 研究能实现RS编码功能的芯片。 在系统架构层， 针对RS编码算法中伽罗华域的乘法运算在硬件实现时存在数据运算量大、 消耗功耗大等问题， 提出基于乘法器因子矩阵的方法对RS编码算法进行优化， 通过将乘法运算转化为减法运算等方式减少数据运算量， 从而降低功耗。 在RTL级和门级层面， 分别在逻辑综合和后端实现中加以约束来实现低功耗设计， 总体功耗可以降低60%左右。 解决了因IC芯片功耗过高导致芯片性能下降， 从而影响芯片正常工作等问题， 为集成电路工艺提供了新的发展方向。
关键词：里所编码； 低功耗设计； 专用集成电路； 逻辑综合
引用格式：ZHANG Pingping, LI Jinming． Low power design and ASIC research of RS code． Journal of Measurement Science and Instrumentation， 2023， 14（2）： 156-163. DOI： 10．3969／j．issn．1674-8042．2023．02．004
[full text view]
