YU Zhiguo1,2， SUN Yi1,2， HUANG Helei1,2， CHE Rao1,2， GU Xiaofeng1,2
（1. Engineering Research Center of IoT Technology Applications Ministry of Education， Jiangnan University, Wuxi 214122， China； 2. School of Internet of Things Engineering, Jiangnan University， Wuxi 214122, China）
Abstract： In computing-in-memory (CIM) chips, analogue computing is more efficient than traditional digital computing due to its low power consumption. As a critical unit in analogue computing, the weighted charge accumulation circuit (WCAC) is challenging to measure because of its complex test pattern and control timing. In order to solve these problems, two key performance metrics: linearity and error distribution, are analysed based on the characteristics of analogue computing architecture and data flow. Further, the design scheme of the test system is proposed, and the test pattern is designed according to target data sets to measure linearities and error distribution. The simulation and measurement results of linearity are 99.79% and 99.11%, respectively. For the error distribution, the mean value of the simulation is -0.06 mV, and the standard deviation is 1.54 mV. The measurement result indicates the same distribution trend as the simulation, with a mean value of 0.37 mV and a standard deviation of 2.07 mV. Overall, the circuit exhibits excellent linearity and calculation accuracy. Furthermore, to evaluate the reliability of the WCAC in network models, the measured error distribution metrics are abstracted into LeNet and AlexNet, respectively, and accuracy experiments are performed on MNIST and CIFAR-10. Experimental results reveal that the accuracies of LeNet on MNIST are reduced by 0.25% and 0.18%, when weight parameters are quantized to 4 bits and 8 bits. The accuracy of AlexNet on CIFAR-10 is reduced by 3.12%, when weight parameters are quantized to 8 bits.
Key words： computing-in-memory (CIM)； weighted charge accumulation circuit (WCAC)； linearity； error distribution
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面向存算一体加权电荷累加电路的线性度和误差分布测试
虞致国1,2， 孙一1,2， 黄合磊1,2， 车饶1,2， 顾晓峰1,2
（1. 江南大学 物联网技术应用教育部工程研究中心， 江苏 无锡 214122； 2. 江南大学 物联网工程学院， 江苏 无锡 214122）
摘要：在存算一体(Computing-in-memory, CIM)芯片中， 相较于传统的数字计算方案， 模拟计算方案由于具有低功耗特性， 可以更高效地完成计算任务。 加权电荷累加电路(Weighted charge accumulation circuit, WCAC)作为模拟计算方案中的关键计算单元， 因复杂的测试激励和控制时序， 在测试方面具有一定挑战性。 本文基于模拟计算架构和数据流的特点分析了线性度和误差分布这两项关键性能参数； 提出了测试系统的设计方案， 并根据目标数据集设计测试激励完成了对线性度和误差分布的测量。 对于线性度， 仿真与测量的结果分别为99.79%和99.11%。 对于误差分布， 仿真结果的平均值为-0.06 mV， 标准差为1.54 mV。 测量结果与仿真结果具有相同的分布趋势， 其均值为0.37 mV， 标准差为2.07 mV。 电路整体呈现优良的线性度和计算精度。 此外， 为了评估WCAC在网络模型中可靠性， 将测量的误差分布结果分别抽象到LeNet和AlexNet中， 并在MNIST和CIFAR-10上进行了准确性实验。 实验结果表明， 在权重参数4比特和8比特量化条件下， LeNet对MNIST的识别准确率分别降低了 0.25%和 0.18%； 在权重参数8比特量化条件下， AlexNet对CAFAR-10的识别准确率降低了3.12%。
关键词：存算一体； 加权电荷累加电路； 线性度； 误差分布
引用格式：YU Zhiguo， SUN Yi， HUANG Helei， et al． Linearity and error distribution measurement of weighted charge accumulation circuit for computing-in-memory． Journal of Measurement Science and Instrumentation， 2023， 14（2）： 174-181. DOI： 10．3969／j．issn．1674-8042．2023．02．006
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