SUN Jingang, LI Jinming
（School of Instruments and Electronics, North University of China, Taiyuan 030051, China）
Abstract： In order to promote the localization of the chip and solve the problem of low decoding efficiency of low density parity check (LDPC) code, taking an LDPC code based on the Consultative Committee for Space Data Systems (CCSDS) standard (8 176,7 154) applied in the near earth space as research object, according to the theory of normalized minimum sum (NMS) decoding algorithm, we design an LDPC decoder with variable scale factor. Firstly, Vivado software is used to write register-transfer level (RTL) code and perform functional simulation. Then, Design Compiler software is used to complete the synthesis of RTL code and generate the gate level netlist required for physical design. Afterwards, Innovus software is used to complete the design of the back-end auto placement route (APR) stage of the chip.When timing check and physical verification of the design are performed by PrimeTime and Calibre software, it can be found that there are 1 132 timing violations of establishment time and retention time as well as 647 design rule violations. By iteratively repairing the violations occurred during timing check and physical verification, the timing meets the requirements and the physical verification violations are cleared. Finally, the graphic data system (GDS) II file is generated, which provides a new research direction for the process of chip localization.
Key words： low density parity check (LDPC); normalized minimum sum decoding (NMS); logic synthesis; IC physical design
References
［1］WU W Y. Research on encoding and decoding algorithm of low orbit satellite communication LDPC code. Harbin: Harbin University of Technology, 2017.
［2］ZHANG L. Research on LDPC code decoding technology. Nanjing: Southeast University, 2020.
［3］JIANG P. Research and optimization of LDPC coding and decoding algorithm. Harbin: Harbin Engineering University, 2020.
［4］LI J M, WANG G D, LIU M X, et al. Research on LDPC coding and decoding algorithm under CCSDS standard. Acta Electronica Sinica, 2020, 48 (11): 2114-2121.
［5］NIU Y, MA Z S. High speed Viterbi decoder based on FPGA. Foreign Electronic Measurement Technology, 2011, 30(8): 63-65.
［6］WANG L Z, LI J M. Design and implementation of LDPC decoder based on FPGA. Electronic Measurement Technology, 2022, 45(1): 22-27.
［7］WANG D T, ZHOU H, QIAN H Y. LDPC adaptive minimum sum decoding algorithm and its FPGA implementation. Computer Science, 2021, 48(S1): 608-612.
［8］WANG G D. Research and design of LDPC codec based on FPGA. ZJONGBEI University, 2021.
［9］LI J M, ZHANG P P, WANG L Z, et al. An FPGA LDPC decoder with optimized scale factor of NMS decoding algorithm. Journal Measurement Science a nd Instrumentation, 2022, 13(4): 398-406.
［10］ZHAO Q Z, WANG Z Y. Application of logic synthesis in digital IC design. Microprocessor, 2013,34(4): 16-18.
［11］WEI D, WANG X H. Analysis and Research on logic synthesis design strategy based on product orientation. China Integrated Circuit, 2018, 27(11): 35-40.
［12］LI X, HU B, WANG X J, et al. Back end design and implementation of a high performance DSP. Integrated Circuit Applications, 2022, 39(4): 228-229.
［13］HAN J N. Hierarchical physical design of a 32-bit CPU core. Dalian University of Technology, 2017.
［14］ZHAO X C, SHI L Z. Back end Design of a Touch and Display Special Chip. Electronic Technology, 2017,46(4): 58-62.
［15］LIU H. Back end design of high-performance graphics chip module based on 7nm process. Xi’an University of Electronic Science and Technology, 2018.
［16］CHEN C Z, AI X, WANG G W. Physical design of digital integrated circuits. Beijing: Science Press, 2008.
LDPC最小和译码算法及其IC物理设计
孙金刚， 李锦明
（中北大学 仪器与电子学院， 山西 太原 030051）
摘要：为促进芯片国产化进程， 解决低密度奇偶校验（Low density parity check, LDPC）码译码效率低下的问题， 以空间数据咨询委员会（The consultative committee for space data systems, CCSDS）标准下的、 应用于近地空间（8 176，7 154）的LDPC码为研究对象， 根据归一化最小和译码（Normalized minimum sum, NMS）算法理论， 设计了一种尺度因子可改变的LDPC译码器。 首先， 利用Vivado软件编写寄存器传输级(Register-transfer level, RTL)代码并进行功能仿真。 其次， 利用Design Compiler工具完成RTL级代码的综合， 以生成物理设计需要的门级网表， 并通过Innovus工具完成对的芯片后端自动布线(Auto placement route, APR)阶段的设计。 在利用Prime Time和Calibre软件分别进行时序检查和物理验证时发现， 存在时序违例1 132条， 设计规则违例647条。 以不断迭代的方式进行修复， 最终消除了违例， 时序和物理设计均满足要求， 并生成了GDS II文件。 该设计可为芯片国产化生产提供新的思路。
关键词：低密度奇偶校验； 最小和译码； 逻辑综合； 集成电路物理设计
引用格式：SUN Jingang, LI Jinming． LDPC minimum sum decoding algorithm and its IC physical design． Journal of Measurement Science and Instrumentation， 2023， 14(1)： 108-115. DOI： 10．3969／j．issn．1674-8042．2023．01．013
[full text view]
