此页面上的内容需要较新版本的 Adobe Flash Player。

获取 Adobe Flash Player

Design of IP core based on AMBA bus


JIA Boxiong, LI Jinming


(School of Instruments and Electronics, North University of China, Taiyuan 030051, China)


Abstract:With the rapid development of integrated circuit (IC) technology, reusable intelligent property (IP) core design is widely valued by the industry. Based on the in-depth study of the functional characteristics of advanced microcontroller bus architecture (AMBA), a design scheme of IP core is presented, and it is divided into the functional modules, and the structural design of the IP core is completed. The relationship between the internal modules of the IP core is clarified, and the top-down design method is used to build the internal architecture of the IP core. The IP core interface module, register module, baud rate module, transmit module, receive module, and interrupt module are designed in detail by using Verilog language. The simulation results show that the designed IP core supports serial peripheral interface (SPI) protocol, the function coverage of IP core reaches 100%, the maximum working frequency reaches 200 MHz, and the resource occupancy rate is less than 15%. The reusable IP core can support multiple data formats, multiple timing transmission modes, and master/slave operation modes, reducing the resource consumption of hardware circuits and having stronger applicability.

Key words:integrated circuit (IC); intelligent property (IP) core; advanced microcontroller bus architecture (AMBA); serial peripheral interface (SPI)


References


[1]ZHU J C. Design and verification of chip TEE module based on AMBA protocol. Ji’nan:Shandong University, 2021.

[2]MA P, LIU P, ZHANG W. UVM-based universal verification platform for AMBA

 bus interface. Computer Systems & Applications, 2021, 30(7):57-69.

[3]WU X F. Research on performance estimation of SoC on-chip bus. Nanjing:Southeast University, 2006.

[4]JIA L. Design and implementation of SMBus controller based on AMBA bus. Chengdu:University of Electronic Science and Technology of China, 2020.

[5]ZHAO J. Realization and verification of IP core of SPI protocol based on AMBA bus. Hefei:University of Science and Technology of China, 2009.

[6]XU Y. Design and verification of high-speed SPI interface circuit. Xi’an:Xidian University, 2020.

[7]GUO P F. Hardware and software co-design in SOC design. Electronic Products, 2004(6):73-75.

[8]YANG Y Q. The design of asynchronous FIFO controller with dual-channel and four-port in the printer. Xi’an:Xidian University, 2014.

[9]CAI S J. Encrypted IP core research on AHB-Lite bus transmission data based on FPGA. Lanzhou:Lanzhou Jiaotong University, 2020.

[10]LI J. The design and implementation of cache based on AMBA bus. Shenyang:Liaoning University, 2021.

[11]LIU P. A low-power MCU design based on AMBA bus of Master Thesis. Chengdu:University of Electronic Science and Technology of China, 2021.

[12]LIU Z X. The verification of FPGA high-speed transceiver PCS IP core based on UVM. Xi’an:Xidian University, 2020.

[13]WANG X Y. Research and design of IP core for industrial ethernet controller based on FPGA. Changchun:Changchun University of Technology, 2020.

[14]SUN Y J. Design and implementation of high-speed SPI interface based on AHB-lite bus. Shenyang:Liaoning University, 2021.

[15]LI Q, YIN Q, YAO S, et al. Design of FIR filter based on FPGA. Information Research, 2021, 47(1):69-73, 78.

 


基于AMBA的IP核设计


贾博雄, 李锦明


(中北大学 仪器与电子学院, 山西 太原 030051)


摘  要:    集成电路技术发展迅速, 使得可复用的知识产权(IP)核设计受到业界的广泛重视。 本文在深入研究高级微控制器总线架构(AMBA)功能特点的基础上, 设计了一种功能相对齐全的IP核, 对其划分功能模块并完成其结构设计, 理清了IP核内部各模块之间的关系, 并采用自顶向下的设计方法搭建出IP核的内部架构。 利用Verilog语言对 IP核接口模块、 寄存器模块、 波特率模块、 发送模块、 接收模块以及中断模块等进行了详细设计。 仿真验证表明, 设计的IP 核支持高级外围总线(APB)总线协议, IP核的功能覆盖率达到100%, 其最高工作频率达到200 MHz, 资源占用率小于15%。 可复用的IP核能够支持多种数据格式、 多种时序传输方式以及主机/从机操作模式, 减少了硬件电路的资源消耗, 具有更强的适用性。


关键词: 集成电路(IC); 知识产权核(IP); 高级微控制器总线架构(AMBA); 串行外设接口(SPI)   


引用格式:JIA Boxiong, LI Jinming. Design of IP core based on AMBA bus. Journal of Measurement Science and Instrumentation, 2022, 13(2):217-224. DOI:10.3969/j.issn.1674-8042.2022.02.011



[full text view]