Zhi-guo1,2, LI Qing-qing1,2, FENG Yang1,2, GU Xiao-feng1,2
(1. Department of Electronic Engineering, Jiangnan University, Wuxi 214122, China;2. Engineering Research Center of IoT Technology Applications of Ministry of Education, Jiangnan University, Wuxi 214122, China)
Abstract: Power consumption in test mode is much higher than that in normal mode, which is prone to causing circuit damage and reducing the yield of chips. To reduce the power dissipation efficiently, a modified linear feedback shift register (LFSR) is designed to decrease switching activity dramatically during the generation of address sequences for memory built-in self-test (MBIST). The address models are generated by a blend of two address generators with an optimized address partition and two distinct controlled clock signals. An address generator circuit for MBIST of 64 k×32 static random access memory (SRAM) is designed to illustrate the proposed scheme. Experimental results show that when the address bus size is 16 bits, compared with the traditional LFSR, the proposed LFSR can reduce the switching activity and dynamic power by 71.1% and 68.2%, respectively, with low area overhead.
Key words: address sequence; linear feedback shift register (LFSR); memory built-in self-test (MBIST); address generator; switching activity
CLD number: TP333doi: 10.3969/j.issn.1674-8042.2020.03.001
References
[1]Querbach B, Khanna R, Puligundla S, et al. Architecture of a reusable BIST engine for detection and auto correction of memory failures and for IO debug, validation, link training, and power optimization on 14-nm SoC. IEEE Design & Test, 2016, 33(1): 59-67.
[2]Mukherjee N, Pogiel A, Rajski J, et al. BIST-based fault diagnosis for read-only memories. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2011, 30(7): 1072-1085.
[3]Naeem A, Jantsch A, Lu Z. Scalability analysis of memory consistency models in NoC-based distributed shared memory SoCs. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2013, 32(5): 760-773.
[4]Goh S H, Chan Y H, Lin Z, et al. Concurrent built-in self-testing under the constraint of shared test resources and its test time reduction. Integration the VLSI Journal, 2017, 59: 198-205.
[5]Harutyunyan G, Shoukourian S, Vardanian V, et al. An effective solution for building memory BIST infrastructure based on fault periodicity. In: Proceedings of IEEE 31st VLSI Test Symposium(VTS), Berkeley, CA, USA, 2013: 1-6.
[6]Goor A J V D, Hamdioui S, Kukner H. Generic, orthogonal and low-cost march element based memory BIST. In: Proceedings of IEEE International Test Conference(ITC), Anaheim, CA, USA, 2012: 1-10.
[7]Park Y, Park J, Han T, et al. An effective programmable memory BIST for embedded memory. IEICE Transactions on Information and Systems, 2009, 92(12): 2508.
[8]Awad A N, Abu-Issa A S. Low power address generator for memory built-in self test. The Research Bulletin of Jordan ACM, 2011, 2(3): 52-56.
[9]Wang J, Hoefler A, Calhoun B H. An enhanced canary-based system with BIST for SRAM standby power reduction. IEEE Transactions on Very Large Scale Integration Systems, 2011, 19(5): 909-914.
[10]Benini L, Bogliolo A, Micheli G D. A survey of design techniques for system-level dynamic power management. readings in hardware/software co-design, 2002, 8(3): 231-248.
[11]Kim Y, Jang J, Son H, et al. Pattern mapping method for low power BIST based on transition freezing method. IEICE Transactions on Information & Systems, 2010, 93-D(3): 643-646.
[12]Abu-Issa A S, Quigley S F. Bit-swapping LFSR for low-power BIST. Electronics Letters, 2008, 44(6): 401-402.
[13]Wang W L, Lee K J. A complete memory address generator for scan based March algorithms. In: Proceedings of IEEE International Workshop on Memory Technology, Design, and Testing, Taipei, Taiwan, China, 2005: 83.
[14]Nourani M, Tehranipoor M, Ahmed N. Low-transition test pattern generation for BIST-based applications. IEEE Transactions on Computers, 2008, 57(3): 303.
[15]Vellingiri G, Jayabalan R. An improved low transition test pattern generator for low power applications. Design Automation for Embedded Systems, 2017, 21(7): 1-17.
[16]Wang S, Gupta S K. DS-LFSR: A new BIST TPG for low heat dissipation. In: Proceedings of International Test Conference, Washington, DC, USA, 1997: 848.
[17]Wang S, Gupta S K. DS-LFSR: A BIST TPG for low switching activity. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2002, 21(7): 842-851.
[18]Yang M H, Kim Y, Park Y, et al. Deterministic built-in self-test using split linear feedback shift register reseeding for low-power testing. IET Computers and Digital Techniques, 2007, 1(4): 369-376.
[19]Ying J C, Tseng W D, Tsai W J. Asymmetry dual-LFSR reseeding for low power BIST. Integration, the VLSI Journal, 2018, 60: 272-276.
[20]Krishna K M, Sailaja M. Low power memory built in self test address generator using clock controlled linear feedback shift registers. Journal of Electronic Testing, 2014, 30(1): 77-85.
基于改进型LFSR的低功耗MBIST地址生成器
虞致国1,2, 李青青1,2, 冯洋1,2, 顾晓峰1,2
(1. 江南大学 电子工程系, 江苏 无锡 214122;2. 江南大学 物联网技术应用教育部工程研究中心, 江苏 无锡 214122)
摘要:存储器进行内建自测试(Mernory built-in self-test, MBLST)时, 其功耗远远高于普通模式下的功耗, 致使电路易损坏并降低了芯片成品率。 针对上述问题, 提出了一种改进的线性反馈移位寄存器, 可在存储器内建自测试的地址序列生成过程中大幅降低翻转率。 首先基于优化的地址分割比生成两个优化的、 可逆的地址生成器, 随后利用时钟信号分别控制两个地址生成电路的时序关系, 最后对64 k×32 SRAM的MBIST的地址生成器进行了仿真验证。 结果表明, 改进的结构与传统的线性反馈移位寄存器(Linear feedback shift register, LFSR)的地址生成结构相比, 地址序列间的翻转率和动态功耗分别降低了71.1%和68.2%, 同时具有面积成本低、 速度快等特点。
关键词:地址序列; 线性反馈移位寄存器; 存储器内建自测试; 地址生成器; 翻转率
引用格式:YU Zhi-guo, Li Qing-qing, FENG Yang, et al. An LFSR-based address generator using optimized address partition for low power memory BIST. Journal of Measurement Science and Instrumentation, 2020, 11(3): 205-210. [doi: 10.3969/j.issn.1674-8042.2020.03.001]
[full text full]