HUANG Xiao-min, ZHANG Zhi-jie
（Key Laboratory of Instrumentation Science & Dynamic Measurement (North University of China), Ministry of Education, Taiyuan 030051， China）
Abstract： The intellectual property (IP) core for inter-integrated circuit (IIC) bus controller is designed using finite state machine (FSM) based on field programmable gate array (FPGA). Not only the data from AT24C02C can be read automatically after power on, but also the data from upper computer can be written into AT24C02C immediately under the control of the IIC bus controller. When it is applied to blast wave overpressure test system, the IIC bus controller can read and store working parameters automatically. In a laboratory environment, the IP core simulation is carried out and the result is accurate. In the explosion field test, by analyzing the obtained valid data, it can be concluded that the designed IP core has good reliability.
Key words： field programmable gate array (FPGA); IIC bus; intellectual property(IP) core; test system
CLD number： TP274Document code： A
Article ID： 1674-8042（2015）01-0013-06 doi： 10.3969/j.issn.1674-8042.2015.01.003
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基于FPGA的IIC总线IP核设计
黄晓敏， 张志杰
（中北大学 仪器科学与动态测试教育部重点实验室， 山西 太原 030051）
摘要:采用FSM在FPGA上设计了IIC总线控制器。 系统上电后它可自动从AT24C02C芯片中读取数据； 从上位机接收到新的数据后， 它也可自动将其存储到AT24C02C中。 该IIC总线控制器应用于冲击波超压测试系统中， 可自动读取和保存重要工作参数。 在实验室环境下， IP核仿真准确。 通过分析爆炸场试验中获得的有效数据， 可以看出该IP核具有很高的可靠性。
关键词:FPGA； IIC总线； IP核； 测试系统
引用格式：HUANG Xiao-min, ZHANG Zhi-jie. Design of IP core for IIC bus controller based on FPGA . Journal of Measurement Science and Instrumentation, 2015, 6（1）: 13-18. ［doi: 10.3969/j.issn.1674-8042.2015.01.003］
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