此页面上的内容需要较新版本的 Adobe Flash Player。

获取 Adobe Flash Player

Multi-seed-encoding BIST Design with Low Power Consumption Based on the Folding Counter

Jian-jun LIU(刘建军)1, Xue-wen PAN(潘学文)2

 

1. School of Information Engineering, Jimei University, Xiamen  361021, China;2. School of Computer Communication Engineering, Hunan University of Science and Engineering, Yongzhou 425100, China

 

Abstract-In this paper, by using the folding counter and linea r feedback shift register, a new vector generator is proposed. The decisive test ing patterns are generated by using the selected fold distance. Then the folding  counter seeds are encoded by the specialized seed encoder and clock gating, the  ineffective patterns do not act upon the circuit under test, these testing patt erns are designed to form a pseudo single input change set, so as to lead to pro minent decreases in power consumption and redundant testing patterns generated b y different seeds, without losing stuck-at fault coverage. Experimental results  based on ISCAS’85 benchmark circuits demonstrate the efficiency of the approac h.

 

Key words-Folding counter; pseudo single; power consump tion

 

Manuscript Number: 1674-8042(2010)03-0276-05

 

dio: 10.3969/j.issn.1674-8042.2010.03.16

 

References

 

[1]S. Hellebrand, J. Rajski, S. Tarnick, S. Venkataraman, B. Courtois,  2005. Built-in test for circuits with scan based on reseeding of multiple-poly nomial linear feedback shift registers. IEEE Transactions on Computers , 44(2): 223-233.

[2]P. Girard, L. Guiller, C. Landrault, S. Pravossoudovitch, 2006. An A djacency-based Test Pattern Generator for Low Power BIST Design. Proceedings of  the 9th Asian Test Symposium, p.459.

[3]P. Girard, L. Guiller, C. Landrault, S. Pravossoudovitch, J. Figureu eras, S. Manich, P. Teixeira, M. Santos, 2005. Low-energy BIST Design: Impact o f the LFSR TPG Parameters on the Weighted Switching Activity. IEEE Int. Symp. on  Circuits and Systems, CD-ROM proceedings.

[4]N. Ahmed, M. H. Tehranipour, M. Nourani, 2004. Low Power Pattern Gen eration for BIST Architecture.  Proc. of the 2004 International Symposium on Cir cuits and Systems, (ISCAS′04), p. 689-692.
 [5]S. Hellebrand, Hua-Guo Liang, H.J. Wunderlich, 2000. A Mixed Mode B IST Scheme Based on Reseeding of Folding Counters. Proceedings of the 2000 IEEE  International Test Conference, p. 778 - 784.
[6]S. Gerstendorfer,  H. J. Wunderlich, 2007. Minimized Power Consumpti on for Scan-based BIST.  Proc. International Test Conference, pp. 77-84.  
[7]N. Nicolici, B. Al-Hashimi, 2003. Power-Constrained Testing of VLS I Circuits. Springer Publishers.

[8]En-min Tan, Sheng-dong Song, Wen-kang Shi, 2007. A vector inserti ng TPG for BIST design with low peak power consumption. High Technolog y Letters, 13(4): 83-87.
 

 

[full text view]