Jhin-fang HUANG(黄进芳)1, Hsui-yen CHUNG(锺戌彦)1, Jiun-yu WEN (温俊瑜)1, Ron-yi LIU(刘荣宜)2
1. Dept. of Electronic Engineering, National Taiwan Universi ty of Science and Technology, Taipei 10672, Taiwan, China; 2. ChungHwa Telecommunication Lab., Taoyuan 32601, Taiwan, China
Abstract-This paper presents a 10-bit 20 MS/s pipelined Ana log-to-Digital Converter(ADC) using op amp sharing approach and removing S ample and Hold Amplifier(SHA) or SHA-less technique to reach the goal of low-p ower consumption. This design was fabricated in TSMC 0.18 μm 1P6M CMOS technology. Measurement results show at supply voltage of 1.8 V, a SFDR of 4 2.46 dB, a SNDR of 39.45 dB, an ENOB of 6.26, and a THD of 41.82 dB are at 1 MHz sinusoidal signal input. In addition, the DNL and INL are 1.4 LSB and 3.23 LSB respectively. The power consumption is 28.8 mW. The core area is 0.595 mm2 and the chip area including pads is 1.468 mm2.
Key words-pipelined ADC; analog-to-digital converter; op amp sharing; SHA-less
Manuscript Number: 1674-8042(2011)01-0047-05
dio: 10.3969/j.issn.1674-8042.2011.01.12
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