SHAN Qing-xiao (单庆晓), YANG Jun (杨俊)
(Mechatronic and Automation School, National University of Defense Technology, Changsha 410073, China)
Abstract：Satellite disciplined clock system (SDCS) composed of satellite timing receiver and local frequency synthesis is widely applied for its high accuracy and low cost. This paper provides a review of SDCS. Key technologies such as phase difference measurement, pulse noise process and frequency calibration are surveyed in detail. Disciplined clock model based on PI controller is built and disciplined process is analyzed. The methods of realizing the disciplined clock circuit are classified and summarized. A prototype based on FPGA is proposed. At last development trend of SDCS is discussed.
Key words：GPS (global positioning system); Beidou system; satellite disciplined clock; timing; frequency calibration
CLD number： P228.41 Document code： A
Article ID： 1674-8042(2012)01-0051-06 doi： 10.3969/j.issn.1674-8042.2012.01.011
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