XIANG Hou-zhen(向厚振)， WANG Peng（王鹏）， YAO Juan（姚娟）， ZHANG Zhi-jie(张志杰)
（School of Information and Communication Engineering, North University of China, Taiyuan 030051, China）
Abstract：After research on the motion estimation algorithm in video coding, a motion estimator algorithm with 1/4 pixel accuracy is implemented based on field-programmable gate array (FPGA). The motion estimation algorithm module is made up of the 1/4 pixel interpolation module with serial input and parallel output, the three step search module and the block matching module, which can use relatively less Wiener filters for interpolation operation. Experiment results show that the hardware design has less consumption of the logical resource, higher stability and lower power consumption.
Key words：H.264/AVC; 1/4 pixel; three-step search; motion estimation; field-programmable gate array (FPGA)
CLD number： TP391.41 Document code： A
Article ID： 1674-8042(2012)04-0341-04 doi： 10.3969/j.issn.1674-8042.2012.04.009
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